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The DSP56000 uses fixed-point math with 24-bit program words and 24-bit data words. It includes two 24-bit registers, which can also be referred to as a single 48-bit register. It also includes two 56-bit accumulators, which add an 8-bit "extension" to what is otherwise similar to the other 24/48-bit registers.
24 bits was selected as the basic word size because it gave the system ample room for processing sound, the 56000's main concern. 24 bits corresponds to a large 144dB dynamic range, and in the eighties A/D and D/A converters rarely exceeded 20 bits anyway. One example is ADSL applications, where filters typically require 20 bits of accuracy. The left-most 4 bits are considered ample headroom or footroom for calculations.
In most designs the 56000 is dedicated to one single task, because digital signal processing using special hardware is mostly real-time and does not allow any interruption. For reasonably demanding tasks which are not time-critical, or more of a simple if-then type, designers normally use a separate CPU or MCU.
The addition of SIMD instructions to most desktop CPUs have meant that dedicated DSP chips like the 56000 have partly retreated from some application fields, but they continue to be used widely in communications and other professional uses. To this end the 56800 series added a complete MCU which created a single-chip "DSPcontroller" solution, while the opposite occurred in the 68456 – a 68000 with a 56000 on it.
A quite prevalent recent model of the 56000 is the 3rd generation 563xx family, which features several models with special applications hardware built-in, like PCI interface logic, CRC processors, or audio companders.